T/E电信级设备

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MACOM公司的T/E电信级产品包括用于T1/E1和T3/E3线路卡的成帧器、LIU和集成的片上系统 (SoC) 解决方案。我们提供高密度和低密度产品,均可用于交换、路由、ADM/MSPP和无线设备中的电信、数据通信和多服务应用。

 

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部件号 订货 描述 ADS & SPICE模型信息 应用笔记 优势 Brightcove视频 兼容部件 目录 数据手册封装概述 硬件手册 设备固件 ESD EVM GUI软件 EVM用户手册 EVM/Reference Design Guides Errata/Non-Conformance External Link 特性 IBIS Files JTAG/BSDL Files Last Time Buys 引线精加工 无铅 MSL 标志 模型数据(Sparameters) 外形图 用户通知 封装 封装类别 产品介绍 产品公告 产品照片 质量报告 ROHS RoHS/IPC报告 Software Programming/User Guides
CN8330 询问 Framer and HDLC Controller
28330-DSH-002-A.pdf
Supports T3/E3 framing modes
Low-power CMOS technology
Operates from a single +5 VDC ±5% power supply
68-pin PLCC or 80-pin MQFP surface-mount package
Supports the LAPD terminal data link and FEAC channel as defined in T1.107a-1989
Average reframe time of less than 1 ms for T3 and less than 250 ?s for E3
Serial or parallel (octet or nibble) interface modes
Framing recovery for M13, C-bit parity, Syntran and G.751 E3 signals
Includes high-speed HDLC controller (52 MHz)
28330-LTB-001-A.pdf
28330-PBD-001-A.pdf
MACOM_general.png
Bt8370 询问 T1/E1 Framer and LIU (Not Recommended for new designs)
询问 Single-chip T1/E1 framer with short/long-haul physical line interface
On-chip physical-line interface compatible with: DSX-1/E1 short-haul signals, DS-1 (T1.403) and ETSI long-haul signals
ISDN primary rate
Frames to popular T1/E1 standards: T1: SF, ESF, SLC? 96, T1DM; E1: PCM-30, G.704, G.706, G.732
Two-frame transmit and receive PCM slip buffers
LTBWOR182.pdf
LTBWOR193.pdf
2XXXX-PCN-003-A.pdf
28XXX-PCN-002-A.pdf
28370-BRF-001-A.pdf
28370-PBD-005-A.pdf
MACOM_general.png
28375g-23_ipc-1752-2_v1.01.pdf
28376G-23_IPC-1752-2_v1.02.pdf
28376g-23_ipc-1752-2_v1.01.pdf
28375g-23_ipc-1752-2_v1.02.pdf
CX28392 询问 2/4/8/16 T1/E1/J1 Framer (Not Recommended for new designs)
询问 28225-EVMD-001-A.pdf
Two, four, eight or sixteen T1/E1/J1 framers in one package
E1: PCM-30, G.704, G.706, G.732, ETS300 011, INS 500
Two-frame transmit and receive PCM slip buffers
Dual HDLC controllers per framer
Single 3.3 V power supply
T1: SF, ESF, SLC ? 96, T1DM,TTC JT(J1)
100202A.ibs
600924A.ibs
100205A.ibs
100204A.ibs
100203A.ibs
28392-LTB-002-A.pdf
LTBWOR185.pdf
28392-LTB-003-A.pdf
2XXXX-PCN-003-A.pdf
CN_080709.pdf
28XXX-PCN-002-A.pdf
28392-BRF-001-A.pdf
MACOM_general.png
CN8370TAP 询问 Telecom Application Software for the Bt8370/5/6 (Not Recommended for new designs)
询问 Fully documented application programming interface (API)
Facility Data Link
Failure Monitoring advanced functions (defect/failure integration and decay)
Failure Monitoring register access
Diagnostics
Register Configuration
Family of products provides broad support and aids technology reuse
Performance Monitoring register access
Performance Monitoring advanced functions (thresholding and 15 min/24 hour statistics accumulation)
Meets applicable ANSI, Bellcore, ATM Forum and ITU-T standards
Operating system independent
Documented ANSI-C source code
LTBWOR182.pdf
TAP-BRF-001-B.pdf
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M28228 询问 27mm & 17mm Octal ATM PHY Solution (Not Recommended for new designs)
28228-DSH-001-C.pdf
500102D.pdf
Integrated 8 port solution, each port is individually configurable for low-speed (T1/E1, T3/E3, xDSL) data inputs
Supports all ATM physical layer cell-alignment processing functions
UTOPIA Level 2, multi-PHY addressing cell-bus interface supports up to 31 PHYs
Microprocessor interface (8-bit data bus for accessing available read/write registers
Programmable bit- or byte- synchronous serial interfaces
LTBWR12.pdf
LTBWR81.pdf
2XXXX-PCN-003-A.pdf
28228-BRF-001-A.pdf
MACOM_general.png
28228g-12_ipc-1752-2_v1.02.pdf
28228-SWG-002-A.pdf
M29374 询问 Quad T1/E1/J1 Transceiver
询问 Complete family of software compatible densities
Hitless protection switching
3 HDLC controllers per channel with SS7 support and V5.2 link ID
Dual 128-bit jitter attenuators per channel
Per channel configuration for J1/E1/T1 frame formatting, line coding and line build out
Selectable per channel impedance matching for 75, 100, 110 and 120O terminations
M2937x-BRF-001-C.pdf
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M28323 询问 3-Port DS3/E3/STS-1 Digital Jitter-Attenuator & STS-1 to DS3/E3 Desynchronizer (Not Recommended for new designs)
询问 High density: up to 12 independent jitter-attenuators and desynchronizers for DS3/ E3 and STS-1 in one package
Small 15 mm BGA package
Power-down control for each channel
One second timer for event latching
Programmable clocking of both inputs and outputs on either edge
Programmable FIFO depth optimal for SONET/SDH
Complies with Telecordia GR-253 and GR-499, ETSI TBR-24 and ANSI T1.105.03b as well as ITU-T G.751, G755, G783 and G.823 standards
Single 3.3 V supply
Ability to independently bypass the JAT for each channel
Ability to dejitter AMI or NRZ input data
Two PRBS generator/detector per channel
Crystal-less jitter attenuation
Low power: <350 mW maximum power consumption
LTBWR207.pdf
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M28324 询问 4-Port DS3/E3/STS-1 Digital Jitter-Attenuator & STS-1 to DS3/E3 Desynchronizer (Not Recommended for new designs)
询问 High density: up to 4 independent jitter-attenuators and desynchronizers for DS3/ E3 and STS-1 in one package
Single 3.3 V supply
Small 15 mm BGA package
Power-down control for each channel
Ability to independently bypass the JAT for each channel
Ability to dejitter AMI or NRZ input data
One second timer for event latching
Two PRBS generator/detector per channel
Programmable clocking of both inputs and outputs on either edge
Crystal-less jitter attenuation
Programmable FIFO depth optimal for SONET/SDH
Low power: <185 mW maximum power consumption
LTBWR207.pdf
28324-BRF-001-A.pdf
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CX28333 询问 3/2/1-Port DS3/E3/STS-1 LIU
28333-DSH-001-A.pdf
28333-EVMD-008-A.pdf
28333-EVMD-010-B.pdf
Receive equalizer requires no user configuration
Meets jitter specifications of Bellcore GR499 and GR253
Large input dynamic range
Full-loopback capability
Programmable pulse filtering to meet cross-connect pulse masks (ANSI T1.102-1993)
28333-LTB-001-A.pdf
CN-111010.pdf
28333-BRF-001-A.pdf
28333-PCN-001-A.pdf
MACOM_general.png
CX28332G-18_IPC-1752-2_v11a_AmkorK_au.pdf
M28333G-34_IPC-1752-2_v1.02.pdf
M28333-34_IPC-1752-2_v11a_AmkorKorea.pdf
CX28333G-18_IPC-1752-2_v11a_AmkorK_au.pdf
CX28333-15_IPC-1752-2_v11a_AmkorK.pdf
CX28332G-18_IPC-1752-2_v11a_AmkorK_au.pdf
M28326 询问 6-Port DS3/E3/STS-1 Digital Jitter-Attenuator & STS-1 to DS3/E3 Desynchronizer (Not Recommended for new designs)
询问 High density: up to 6 independent jitter-attenuators and desynchronizers for DS3/ E3 and STS-1 in one package
Single 3.3 V supply
Small 15 mm BGA package
Power-down control for each channel
Ability to independently bypass the JAT for each channel
Ability to dejitter AMI or NRZ input data
One second timer for event latching
Two PRBS generator/detector per channel
Programmable clocking of both inputs and outputs on either edge
Crystal-less jitter attenuation
Programmable FIFO depth optimal for SONET/SDH
Low power: <250 mW maximum power consumption
LTBWR207.pdf
28326-BRF-001-A.pdf
MACOM_general.png
M28320DRV 询问 Device Driver Software (Not Recommended for new designs)
询问 Initialization
Event Processing
Register Configuration
LTBWR30.pdf
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M29378 询问 Octal T1/E1/J1 Transceiver
询问 Complete family of software compatible densities
Hitless protection switching
3 HDLC controllers per channel with SS7 support and V5.2 link ID
Dual 128-bit jitter attenuators per channel
Per channel configuration for J1/E1/T1 frame formatting, line coding and line build out
Selectable per channel impedance matching for 75, 100, 110 and 120O terminations
M2937x-BRF-001-C.pdf
MACOM_general.png
M28328 询问 8-Port DS3/E3/STS-1 Digital Jitter-Attenuator & STS-1 to DS3/E3 Desynchronizer (Not Recommended for new designs)
询问 High density: up to 12 independent jitter-attenuators and desynchronizers for DS3/ E3 and STS-1 in one package
Complies with Telecordia GR-253 and GR-499, ETSI TBR-24 and ANSI T1.105.03b as well as ITU-T G.751, G755, G783 and G.823 standards
Single 3.3 V supply
Small 15 mm BGA package
Power-down control for each channel
Ability to independently bypass the JAT for each channel
Ability to dejitter AMI or NRZ input data
One second timer for event latching
Two PRBS generator/detector per channel
Programmable clocking of both inputs and outputs on either edge
Crystal-less jitter attenuation
Programmable FIFO depth optimal for SONET/SDH
Low power: <350 mW maximum power consumption
LTBWR207.pdf
MACOM_general.png
M28320 询问 12-Port DS3/E3/STS-1 Digital Jitter-Attenuator & STS-1 to DS3/E3 Desynchronizer (Not Recommended for new designs)
询问 28320-ERR-001-A.pdf
High density: up to 12 independent jitter-attenuators and desynchronizers for DS3/ E3 and STS-1 in one package
Small 15 mm BGA package
Power-down control for each channel
One second timer for event latching
Programmable clocking of both inputs and outputs on either edge
Programmable FIFO depth optimal for SONET/SDH
Complies with Telecordia GR-253 and GR-499, ETSI TBR-24 and ANSI T1.105.03b as well as ITU-T G.751, G755, G783 and G.823 standards
Single 3.3 V supply
Ability to independently bypass the JAT for each channel
Ability to dejitter AMI or NRZ input data
Two PRBS generator/detector per channel
Crystal-less jitter attenuation
Low power: <350 mW maximum power consumption
LTBWR30.pdf
LTBWR207.pdf
2XXXX-PCN-003-A.pdf
28320-BRF-001-A.pdf
Macom_gen.png
M29372 询问 Dual T1/E1/J1 Long Haul / Short Haul Transceiver
询问 Complete family of software compatible densities
Hitless protection switching
3 HDLC controllers per channel with SS7 support and V5.2 link ID
Dual 128-bit jitter attenuators per channel
Per channel configuration for J1/E1/T1 frame formatting, line coding and line build out
Selectable per channel impedance matching for 75, 100, 110 and 120O terminations
M2937x-BRF-001-C.pdf
MACOM_general.png
M29372G-11_IPC-1752-2_v1.1a.pdf
M29306 询问 6-Port DS3/E3/STS-1 Integrated Line Termination Device for ATM, Packet Processing and TDM Transport Networks
询问 High integration - LIUs with DJAT, T3/E3, STS-1 framers/mappers, STS-12/STM-4 framer, ATM & HDLC processors
Pattern generator/detector for BERT
Embedded CLADs for supported line rates
T3/E3/STS-1 payload access
Parallel 8-bit, 77.76 MHz TDM telecom bus
Easy implementation - TAP software + high integration = faster time-to-market
Comprehensive loopbacks
Fractional T3/E3 support
ATM/packet interfaces: SPI-3 8-bit 25-104 MHz, UTOPIA Level 2/POS-PHY Level 2, 16-bit 25-50 MHz
Flexibility - mix ATM, TDM and packet as well as T3, E3 and STS-1 services on one device
CN_092910-3[1].pdf
29306-BRF-001-A.pdf
619512A.jpg
M29306TAP 询问 Telecom Application Software
询问 Register configuration
Diagnostics
Failure monitoring advanced functions (defect/failure integration and decay)
Falure monitoring register access
Performance monitoring advanced functions (thresholding and 15 min/24 hour statistics accumulation)
Performance monitoring register access
TAP-BRF-001-B.pdf
MACOM_general.png
M29323 询问 3/6-Port DS3/E3/STS-1 Integrated Line Termination Device for Transport Networks
询问 High integration - LIUs with DJAT, DS3/E3 framers/mappers, STS-1 framers/mappers, STS-12/STM-4 framer
Easy implementation -TAP software + high integration = faster time-to-market
Embedded CLADs for supported line rates
Parallel 8-bit, 77.76 MHz TDM telecom bus
Comprehensive loopbacks
Pattern generator/ detector for BERT
Flexibility - mix DS3, E3 and STS-1 on one device
CN_092910-3[1].pdf
29323-BRF-001-A.pdf
619516A.jpg
M29320 询问 12-Port DS3/E3/STS-1 Electrical Integrated Line Termination Device for Transport Networks
询问 High-density - 12 DS3/E3/STS-1 LIUs with jitter attenuation/ desynchronization
Dual embedded OC-12 CDRs
12 STS-1 SONET/SDH framers
Dual high speed serial LVDS 622 MHz interface
STS-12/STM-4 SONET/SDH TDM framer
24 DS3/E3 framers
12 DS3/E3 mappers/demappers
Parallel 8-bit, 77.76 MHz TDM Telecom Bus
2XXXX-PCN-004-A.pdf
CN_092910-3[1].pdf
29320 Package PCN 051410b.pdf
293XX Package PCN 051410.pdf
29320-BRF-001-A.pdf
29320-PBD-002-A.pdf
Macom_gen.png
M29320-14_IPC-1752-2_v1.02.pdf
M29320G-14_IPC-1752-2_v1.1a_ASEK.pdf
M29320TAP 询问 Telecom Application Software
询问 Register configuration
Diagnostics
Failure monitoring advanced functions (defect/failure integration and decay)
Falure monitoring register access
Performance monitoring advanced functions (thresholding and 15 min/24 hour statistics accumulation)
Performance monitoring register access
TAP-BRF-001-B.pdf
29320-PBD-002-A.pdf
MACOM_general.png
M28335 询问 12-Port DS3/E3/STS-1 LIU
询问 12 separate DS3/E3/STS-1 line interfaces in a single 35 mm TBGA package
Single 3.3 V power supply
Full diagnostic loopback capability
Per channel transmit monitor with external monitor points and test function
Programmable loss of signal threshold
Low power
Integrated B8ZS (T3) or HDB3 (E3) encoders/decoders with line code violation (LCV) indication
Parallel and serial microprocessor interfaces
628702A.pdf
28335-BRF-001-B.pdf
MACOM_general.png